The development of new high resolution CRTs capable of dissipating up to 36 watts at the anode has created the need for a high voltage power supply capable of providing 75 watt peaks and a 36 watt continuous signal to the anode output with high efficiency under heavy loads in order to reduce both electrical and thermal component stress. Previous high voltage power supply designs developed less output power and, therefore, were not as concerned with thermal and electrical stress due to low efficiencies. The invention is designed to work as part of a resonant flyback high voltage supply such as the type described in "Designing Ultra-Efficient High Voltage supplies Using a High-Frequency Frequency Resonant Flyback Technique", William Santelmann, Jr., 1982 Proceedings of Powercom 9, G1-2, p.1 (hereinafter referred to as "Santelmann"). Another concept which serves as background for the invention is detailed by T. K. Phelps in "Optimizing the design of Switch-Mode Power Conditioners Using Capacitive Voltage Multipliers", 1981 Proceedings of Powercon 8, I-1, pp. 1-7.
One type of known power supply operates at a fixed frequency. To meet increasing load requirements, a power switch, usually an FET, must turn on at increasing drain voltages. This allows more charging time for the coupled inductor.
Other known supplies operate at a fixed frequency. In such supplies, increased load requirements are met by producing an increased gate voltage on the power switch FET. This provides more current to the coupled inductor and in turn more energy to the multiplier stage. The shortcomings of such known power supplies stem from their fixed frequency operation.
One such deficiency of prior art power supplies that increased load requirements are met by increasing coupled inductor charging time by turning on the power switch FET at higher voltage levels on the flyback waveform thereby dropping greater voltages across the FET. FET power dissipation rapidly increases under increasing loads and becomes the limiting factor in power efficiency.
In another type of known power supply, the FET gate voltage is varied in order to regulate the FET's drain-source resistance, Rds, which in turn controls the coupled inductor charging current. At low loads, the gate voltage approaches Vth thereby driving Rds up, thereby dissipating needless power in the FET.
The invention overcomes the deficiencies in the prior art by using variations in frequency to meet varying anode loads. By reducing the frequency as load increases, the invention allows the flyback waveform to complete its resonant cycle before turning on the power switch FET. The power switch FET is turned on when the drain voltage decreases to 0 volts, thus eliminating the extra power dissipation encountered in previous designs. Santelmann, for example, does not recognize the critical timing required to turn on the gate of the power switch FET at the proper time. Santelmann teaches at Page 7, fifth paragraph, that the gate of the power switch FET may be turned on at any time when negative current flows through it (see also Snatelmann FIG. 2). While this unsynchronized approach may appear to be somewhat acceptable under light load conditions, the present invention recognizes that it will not satisfy full load conditions because the amount of "dead time" between the drain current beginning a positive rise and the drain voltage discharge of the circuit to 0 volts as shown in FIG. 7B herein and FIG. 8 of Santelmann, for example, is extremely short and, in fact, the drain current never goes negative. The invention recognizes for the first time that it is critical that the power switch FET, be turned on when the drain voltage has fallen to its minimum value, determined by a greatly reduced dv/dt on the falling slope of the drain waveform. This feature of the invention is explained in detail below with reference to FIGS. 3-7.
The power switch FET gate drive voltage on the supply of the invention turns the power switch FET on fully thereby driving the FET Rds parameter to its specified minimum. Some types of known supplies do not drive the gate full on, therefore Rds is not driven to its minimum specified limit. Thus, FET power loss due to coupled inductor charging current through Rds increases thereby limiting the efficiency of the power supply.